Title :
An on-chip double-bit error-correcting code for three-dimensional dynamic random-access memory
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
An error-correcting code is described which can correct up to two soft errors on each work line within a DRAM (dynamic random-access memory) chip. Three dimensional DRAM chips with trench-type capacitors are vulnerable to double-bit soft errors when an alpha particle strikes at the intervening space between two vertical capacitors setting off a plasma discharge between them. The author presents a systematic study of soft-error related problems, and discusses the methodologies to correct the double-bit memory-cells upsets by using on-chip ECC (error-correcting code) circuits. A comprehensive study is made to estimate the improvement in soft-error rate (SER) and mean time between failure (MTBF) by the proposed ECC technique. The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed using combinational enumeration
Keywords :
VLSI; error correction codes; integrated circuit testing; integrated memory circuits; random-access storage; DRAM; MTBF; RAM; VLSI; alpha particle; combinational enumeration; double-bit soft errors; mean time between failure; multiple-bit errors; on-chip double-bit error-correcting code; plasma discharge; soft-error rate; three-dimensional dynamic random-access memory; Alpha particles; Capacitors; Circuit faults; Computer errors; Error correction; Error correction codes; Microelectronics; Plasmas; Random access memory; Very large scale integration;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207812
