DocumentCode
3111102
Title
A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability
Author
Gupta, Sandeep K. ; Pradhan, Dhiraj K.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
1988
fDate
12-14 Sep 1988
Firstpage
329
Lastpage
342
Abstract
A coding theory framework is developed for analysis and synthesis of compression techniques in the built-in self test (BIST) environment. Using this framework, exact expressions are derived for the linear feedback shift register aliasing probability. These are shown to be more accurate than earlier ones. Also shown is that there exist compression techniques for which the aliasing probability can be reduced to zero asymptotically. An error model is presented that incorporates the effects of faults on output response. It is shown that the coding theory framework correlates well with this proposed error model. A signature analysis technique is presented, which achieves smaller aliasing probability than other recently proposed schemes
Keywords
data compression; encoding; integrated circuit testing; logic testing; probability; shift registers; BIST; aliasing probability; built-in self test; coding theory; compression; effects of faults; error model; linear feedback shift register; signature analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Codes; Costs; DH-HEMTs; Data compression; Hardware;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-8186-0870-6
Type
conf
DOI
10.1109/TEST.1988.207819
Filename
207819
Link To Document