A realistic self-test machine for static random access memories

Author

Dekker, Rob ; Beenker, Frans ; Thijssen, Loek

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1988

fDate

12-14 Sep 1988

Firstpage

353

Lastpage

361

Abstract

A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of hardware overhead and performance loss. Self-test reduces the possibilities for diagnostic tests. A form of scan test remains necessary in spite of a self-test implementation. This self-test design offers full scan test facilities of both the SRAM and the self-test logic itself. This version of the SRAM self-test is currently being implemented in a number of digital signal processing chips and will, after a final evaluation, be used for a broad scope of designs

Keywords

automatic test equipment; automatic testing; digital signal processing chips; fault location; integrated circuit testing; integrated memory circuits; at a retention test; automatic testing; diagnostic tests; digital signal processing chips; fault-detection; linear test algorithms; scan test; self-test logic; self-test machine; static random access memories; Automatic testing; Built-in self-test; Hardware; Logic design; Logic testing; Performance loss; Random access memory; SRAM chips; Signal processing algorithms; Test facilities;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207821

Filename

207821