DocumentCode :
311154
Title :
Fast addition using a new number system
Author :
Hashemian, Reza
Author_Institution :
Northern Illinois Univ., DeKalb, IL, USA
fYear :
1996
fDate :
3-6 Nov. 1996
Firstpage :
884
Abstract :
A new approach is proposed for the design of high speed adders. Unlike the traditional approach here the attention is on the data format. It is shown that converting one of the operands to a specific type of ternary numbers, called signed digit number, makes the addition faster by eliminating the carry term. The problem with this approach is the need for data conversion from 2´s complement to SD number format and the reverse. This approach is later modified and a procedure is presented that produces the sum term even without any data conversion and with no formal carry propagation. The trade off is, of course, addition of some extra logical operations and bit-pattern search operation.
Keywords :
adders; data conversion; digital arithmetic; 2´s complement; bit pattern search operation; data conversion; data format; fast addition; high speed adder design; logical operations; number system; operands; signed digit number; ternary numbers; Data conversion; Digital arithmetic; Propagation delay;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
ISSN :
1058-6393
Print_ISBN :
0-8186-7646-9
Type :
conf
DOI :
10.1109/ACSSC.1996.599071
Filename :
599071
Link To Document :
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