Title :
2-1 redundant addition with threshold logic
Author :
Cotofana, Sorin ; Vassiliadis, Stamatis
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
We investigate threshold based networks performing 2-1 addition using redundant binary operand representations. In particular we concern with establishing the networks with the smallest network depth assuming small weight and fan-in values. First we propose a depth-4 implementation and we show that the 2-1 addition can be computed by a threshold network with the size in the order of O(n) and with O(1) weight and fan-in values. Consequently, we prove that the network depth can be reduced to 2 and yet maintain the O(n) size and O(1) weight and fan-in asymptotic complexities.
Keywords :
adders; digital arithmetic; redundant number systems; threshold logic; 2-1 redundant addition; asymptotic complexity; network depth; network size; redundant binary operand representations; small fan-in values; small weight values; threshold based networks; threshold logic; Boolean functions; CMOS logic circuits; CMOS process; CMOS technology; Computer networks; Equations; Input variables; Neurons; Semiconductor device modeling;
Conference_Titel :
Signals, Systems and Computers, 1996. Conference Record of the Thirtieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-8186-7646-9
DOI :
10.1109/ACSSC.1996.599072
