Variations on multioperand addition for faster logarithmic-time tree multipliers

A carry-free addition process for radix-2 numbers with the digit set [0, 3] is introduced and applied to the synthesis of tree multipliers using multi-operand adders built as binary trees. Such binary trees are more regular than standard carry-save adder (Wallace or Dadda) trees and thus offer advantages in terms of VLSI realization. We show that certain designs derived from binary stored-double-carry numbers with digit set [0, 3] compare favorably with previously proposed multipliers using binary-tree multioperand addition schemes based on reducing pairs of carry-save numbers with (4, 2) counters or combining pairs of borrow-save numbers using binary signed-digit adders. The advantages are particularly pronounced for word lengths that are at or close to halfway between consecutive powers of 2 (e.g. around 12, 24, or 48 bits).