DocumentCode
3111619
Title
Power consumption reduction for configuration SRAM of field programmable gate arrays
Author
Matyushin, Denis V. ; Kurganskii, Sergei I.
Author_Institution
Eng. & Design Center Electron., Joint Stock Co., Voronezh, Russia
fYear
2011
fDate
June 30 2011-July 4 2011
Firstpage
143
Lastpage
145
Abstract
This article describes a method of reducing power consumption for configuration SRAM cells. Modification of the SRAM cell is performed taking into account special characteristics of FPGA configuration memory. Characteristics of the cells are summarized.
Keywords
SRAM chips; field programmable gate arrays; FPGA configuration memory; SRAM cells; field programmable gate arrays; power consumption reduction; Field programmable gate arrays; Inverters; Leakage current; Noise; Random access memory; Threshold voltage; Transistors; FPGA; Leakage current; asymmetric SRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Micro/Nanotechnologies and Electron Devices (EDM), 2011 International Conference and Seminar of Young Specialists on
Conference_Location
Erlagol, Altai
Print_ISBN
978-1-61284-793-1
Type
conf
DOI
10.1109/EDM.2011.6006917
Filename
6006917
Link To Document