Enhancing random-pattern coverage of programmable logic arrays via masking technique

A testable design is presented of programmable logic arrays (PLAs) with high fault coverage for random test patterns. The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. To clarify the effect of the masking technique, an experiment was performed in which eight large PLAs were modified by adding various sizes of mask arrays, and then performing fault simulation with random patterns for those random-pattern test coverage curves. It was found that fault coverage could be significantly enhanced by the proposed masking technique with very low area overhead