• DocumentCode
    3111736
  • Title

    An expert test program generation system for per-pin testers

  • Author

    Walter, A. ; Kleinman, Y. ; Edelshteyn, L. ; Gartner, J.

  • Author_Institution
    IBM, Hopewell Junction, NY, USA
  • fYear
    1988
  • fDate
    12-14 Sep 1988
  • Firstpage
    665
  • Lastpage
    668
  • Abstract
    The development is discussed of a rules-based automatic test-program generator (ATPG) that integrates IBM´s CAD (computer-aided design) system with a per-pin tester. The authors describe the versatility of the ATPG that gleans test patterns and the logic model from the CAD system, merges produce technology characteristics and generates a complete test program that verifies the electrical, functional, and timing integrity of the device under test
  • Keywords
    automatic programming; automatic testing; circuit CAD; expert systems; logic testing; CAD; IBM; automatic test-program generator; expert test program generation; logic model; per-pin testers; Automatic test pattern generation; Automatic testing; Character generation; Design automation; Logic design; Logic devices; Logic testing; System testing; Test pattern generators; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1988. Proceedings. New Frontiers in Testing, International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-8186-0870-6
  • Type

    conf

  • DOI
    10.1109/TEST.1988.207850
  • Filename
    207850
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3111736