Title :
Robust tests for parity trees
Author :
Kundu, Sandip ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
Tests to detect line stuck-at and transistor stuck-open faults in CMOS binary parity trees are considered. The main objective was to derive bounds on test sequences and test sequences that detect all single faults, even in the presence of circuit delays. It is shown that the desired robustness of test requires tests whose lengths are proportional to the depth of the trees under test, in contrast to earlier used tests of constant length, in which robustness was not required. The results derived give exact bounds for complete trees, but similar results for incomplete trees need further investigations
Keywords :
CMOS integrated circuits; delays; integrated logic circuits; logic testing; network topology; CMOS binary parity trees; circuit delays; logic testing; network topology; robustness; stuck at fault; test sequences; transistor stuck-open faults; Array signal processing; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Fault detection; Linear circuits; Logic circuits; Logic testing; Robustness;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207852