Stuck-open and transition fault testing in CMOS complex gates

A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used to determine the stuck-open fault coverage of a given test set. Multiple stuck-open faults are handled implicitly. Thus, results are not invalidated in the presence of untested or untestable faults. Robust test sets can be generated easily. The method can be used both for test generation and for fault diagnosis. Experimental results for multiple stuck-open fault coverage for ten benchmarking circuits are presented and compared. In particular, coverage figures for both robust and nonrobust test sets are presented