A novel systolic design for fast computation of the discrete Hartley transform

The discrete Hartley transform (DHT), first introduced by Bracewell (1983), has been emerging as a new tool for the analysis, design, and implementation of digital signal processing algorithms and systems. This paper presents a novel systolic array with log/sub 2/N multipliers and 3log/sub 2/N adders for computing the N-point DHT, where N is a power of two. The architecture reaches a throughput of one complete N-point transform per N clock cycles, i.e., one transform sample per clock cycle. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. Compared to existing related systolic/regular designs, the proposed one gains improvements in area-time complexity.