Circular BIST with partial scan

Author

Pradhan, M.M. ; O´Brien, E.J. ; Lam, S.L. ; Beausang, J.

Author_Institution

AT&T, Princeton, NJ, USA

fYear

1988

fDate

12-14 Sep 1988

Firstpage

719

Lastpage

729

Abstract

A BIST (built-in self test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (circuit under test) by configuring the circular path as a partial scan chain. A CAD (computer-aided-design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated, and experimental results are presented

Keywords

automatic testing; fault location; flip-flops; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; sequential circuits; CAD; built-in self test; circuit under test; circular path; deterministic tests; fault coverage; flip-flops; heuristics; logic testing; partial scan; partial scan chain; random test; sequential logic circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design automation; Design for testability; Flip-flops; Performance evaluation; Sequential analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1988. Proceedings. New Frontiers in Testing, International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-8186-0870-6

Type

conf

DOI

10.1109/TEST.1988.207857

Filename

207857