DocumentCode
3112035
Title
A median filter FPGA with Harvard Architecture
Author
Junxia, Zhao ; Botao, Zheng ; Hongjun, Liu
Author_Institution
Electron. Eng. Dept., Sanjiang Univ., Nanjing, China
fYear
2011
fDate
26-28 March 2011
Firstpage
50
Lastpage
51
Abstract
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part of the multi-image processing chip.
Keywords
computer architecture; field programmable gate arrays; image processing; median filters; microprocessor chips; Harvard architecture; Von Neumann architecture; median filter FPGA; multi-image processing chip; Algorithm design and analysis; Digital signal processing; Field programmable gate arrays; Filtering algorithms; Hardware; Noise; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Science and Technology (ICIST), 2011 International Conference on
Conference_Location
Nanjing
Print_ISBN
978-1-4244-9440-8
Type
conf
DOI
10.1109/ICIST.2011.5765209
Filename
5765209
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