A fast placement and global routing integrated algorithm for hierarchical FPGAs

Traditional physical design of FPGAs is usually divided into 2 phases, placement and routing. While it simplifies design modelling and algorithm implementation, some problems such as mismatches between the two will also occur when a valid placed circuit can´t be globally routed. The mismatches can significant increase the overall runtime of the physical design. A new placement and global routing integrated algorithm is proposed in order to reduce these mismatches. By immediately applying a global routing feedback to each placement step, the invalid placement step can be found and re-placed. Finally, a valid placed, globally routed circuit is obtained ready for the following detailed routing. This algorithm also takes advantages of the architectural features of the new hierarchical FPGAs and employs clustering at each placement step. As the clustering algorithm is hierarchical in its essence, it is very similar with the FPGA in structure. As a result, the proposed algorithm is very fast in runtime due to all these facts. The experimental results show that a very large circuit can be placed and globally routed very quickly in just a few seconds.