A low time complexity defect-tolerance algorithm for nanoelectronic crossbar

Emerging nanoelectronic technologies are expected to extend the conventional integrated circuits beyond CMOS. However, the bottom-up self-assembly fabrication process of nanoelectronic devices results in higher defect density. Thus, crafted defect-tolerance techniques are urgently needed. In this paper, we present a low time complexity algorithm for application-independent defect-tolerance of nanoelectronic crossbars. The algorithm improves the performance through mixing the key ideas from two state-of-the-art algorithms. The algorithm offers similar (above 90%) defect-free subcrossbar sizes compared to the current best algorithm as the results show over a set of samples with various crossbar sizes and defect densities, but the time complexity is reduced from O(n³) down to O(n²). Thus, our algorithm is more suitable for defect-tolerance of reconfigurable nanoelectronic crossbar due to the per-chip basis.