Title :
Bridge: a behavioral synthesis system for VLSI
Author :
Tseng, Chia-Jeng ; Wei, Ruey-sing ; Rothweiler, Steven G. ; Tog, M.M. ; Bose, Ajoy K.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
Bridge is a behavioral synthesis system in which a variable in a behavioral description can be either a storage element or a signal. The impact of treating a variable as a signal on lifetime analysis is discussed. The feature of supporting both signals and registers for program variables facilitates systematic tradeoffs between cost and performance. Intelligent bindings of the variables in a behavioral description to registers and signals not only reduce the implementation cost but also improve the circuit performance. Experimental data for the descriptions of three telecommunication circuits are presented
Keywords :
VLSI; circuit CAD; Bridge; VLSI; behavioral synthesis system; circuit performance; implementation cost; lifetime analysis; program variables; storage element; systematic tradeoffs; telecommunication circuits; Bridge circuits; Circuit optimization; Control system synthesis; Control systems; Costs; Design optimization; Registers; Signal synthesis; Telecommunication control; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20788
