Concurrent off-phase built-in self-test of dormant logic

Concurrent off-phase built-in self-test is described, which permits the operation of built-in self-test hardware designed for offline testing concurrently with normal system operations. It takes advantage of the logic dormancy characteristic of designs which use two-phase clocking. This method provides online detection for permanent faults and can be used in conjunction with a time-redundant concurrent test method to detect transient and intermittent as well as permanent faults. Also, the method provides guaranteed self-test for self-checking circuits. Concurrent off-phase BIST requires duplication of storage elements but otherwise makes use of BIST hardware used for noncurrent, offline testing. Also, there may be an associated time penalty which, for the given example of CMOS technology with a symmetric phase clock period of 50 ns, is estimated to be an 11.6% increase in the clock period