Title :
Testability using random access test register
Abstract :
Design for testability in VLSI circuits is described using random-access test registers and externally loaded microinstructions. Significant improvements over the scan method in terms of die size and at-speed testing are claimed. Implementation is highly structural and simple, and provides a powerful tool for design debugging and fault diagnostic
Keywords :
VLSI; automatic testing; fault location; integrated circuit testing; IC testing; VLSI circuits; automatic testing; design debugging; die size; externally loaded microinstructions; fault diagnostic; fault location; random access test register; Automatic testing; Circuit faults; Circuit testing; Clocks; Decoding; Graphics; Logic devices; Logic testing; Registers; Semiconductor device testing;
Conference_Titel :
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-0870-6
DOI :
10.1109/TEST.1988.207890
