A 1.8 mW 2 MHz signal bandwidth continuous-time sigma-delta modulator

Author

Chen, Xiao-fei ; Xu, Jin-bo ; Zou, Xue-cheng ; Lin, Shuang-xi

Author_Institution

Dept. of Electron. Sci. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

2011

fDate

26-28 March 2011

Firstpage

221

Lastpage

224

Abstract

A fully differential feedback third-order continuous-time sigma-delta modulator suitable for Mega Hertz wireless communication is presented. Some design optimizations mainly regarding power consumption are demonstrated. The proposed single-bit modulator clocked at 128 MHz achieves 2 MHz signal bandwidth, 11 bits of resolution, 68 dB signal-to-noise ratio and 66 dB dynamic range. Designed in 0.18 μm CMOS process, the sigma-delta modulator consumes 1.8 mW from a 1.8 V single supply, occupying a 0.16 mm² chip area.

Keywords

CMOS integrated circuits; circuit feedback; logic design; sigma-delta modulation; CMOS process; bandwidth 2 MHz; design optimizations; frequency 128 MHz; fully differential feedback third-order continuous-time sigma-delta modulator; mega Hertz wireless communication; power 1.8 mW; power consumption; single-bit modulator; size 0.18 mum; voltage 1.8 V; word length 11 bit; Bandwidth; Clocks; Gain; Modulation; Power demand; Sigma delta modulation; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science and Technology (ICIST), 2011 International Conference on

Conference_Location

Nanjing

Print_ISBN

978-1-4244-9440-8

Type

conf

DOI

10.1109/ICIST.2011.5765241

Filename

5765241