• DocumentCode
    3112738
  • Title

    Defining a standard for fault simulator evaluation

  • Author

    Al-Arian, Sami A. ; Kwiat, Kevin A.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    1988
  • fDate
    12-14 Sep 1988
  • Firstpage
    1001
  • Abstract
    An acceptable standard is developed for relating fault simulator results from different simulators. Each simulator should verify the good circuit and evaluate the effectiveness of the generated test patterns (fault coverage). A hypothetical standard set of characteristics are proposed and each of the simulators are redefined in terms of the standard. These recommendations for evaluating these fault simulators and relating them to the standard include: the use of the same circuit topology (structure) and same ordered test vectors. However, the use of fault classes as a basis for evaluating the fault coverage is the major result of this effort
  • Keywords
    automatic testing; digital simulation; fault location; integrated circuit testing; logic testing; military computing; military equipment; network topology; standards; IC testing; circuit topology; fault coverage; fault simulator evaluation; generated test patterns; military equipment; ordered test vectors; standard; Clocks; Fault detection; Sequential analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1988. Proceedings. New Frontiers in Testing, International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-8186-0870-6
  • Type

    conf

  • DOI
    10.1109/TEST.1988.207896
  • Filename
    207896