Title :
Layout automation of CMOS analog building blocks with CADENCE
Author :
Dzahini, D. ; Gaffiot, F. ; Boutherin, B. ; Le Helley, M.
Author_Institution :
LEAME, CNRS, Ecole Centrale de Lyon, Ecully, France
fDate :
29 May-1 Jun 1990
Abstract :
Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE
Keywords :
CMOS integrated circuits; application specific integrated circuits; cellular arrays; circuit layout CAD; linear integrated circuits; CADENCE; CMOS analog building blocks; SKILL language; capacitors; design of analog CMOS circuits; design rules; electrical parameters; layout automation; layout of CMOS cells; mixed-mode ASICs; placement; resistors; routing; set of tools; shape description; transistor; Automation; Circuits; Electric variables; Graphics; Irrigation; Layout; MOS capacitors; MOSFETs; Resistors; Shape;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207915
