Analog circuit synthesis with simplified knowledge acquisition and fast transistor sizing

Presents a system for analog CMOS circuit synthesis. It tries to overcome shortcomings of the rule based expert system approach at the stage of the circuit composition and provides sized netlists without simulation based optimization being necessary. A functional description of the required circuit is used to compose an application-appropriate schematic out of a set of parameterizable subcells. Transistor sizing is done with a table model which accurately relates small-signal transistor parameters to widths and lengths. The small-signal parameters are found from circuit specification using first order model equations. The table may be constructed through measurements or with presimulated values. The latter allows one to take parasitic layout effects into account in advance. A design example is presented