VLSI architecture of forward and inverse quantization modules of H.264 for HD transmission

Author

Mukherjee, Rohan ; Kumar, E. Sandeep ; Chakrabarti, Indrajit ; Sengupta, Sabyasachi

Author_Institution

Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India

fYear

2013

fDate

13-15 Dec. 2013

Firstpage

1

Lastpage

4

Abstract

The latest video compression standard H.264 has introduced novel algorithms for quantization and inverse quantization processes. In this paper, new hardware architectures are proposed for the forward quantizer and inverse quantizer blocks for real-time video processing. Implemented in Xilinx 14.1, Virtex-5 technology, the designed architectures for quantizer and its inverse have a critical path delay of 11.62 ns and 10.87 ns respectively. The proposed designs when integrated with other modules of transform domain of H.264 can achieve the speed requirement of HD-1080 video format at 30 frames per second.

Keywords

VLSI; data compression; quantisation (signal); video codecs; video coding; H.264 standard; HD transmission; HD-1080 video format; VLSI architecture; Virtex-5 technology; Xilinx 14.1 technology; critical path delay; forward quantization modules; forward quantizer; hardware architecture; inverse quantization modules; inverse quantizer; real time video processing; time 10.87 ns; time 11.62 ns; video compression standard; Arrays; Image reconstruction; Quantization (signal); Read only memory; Standards; Transforms; FPGA; Forward Quantization; H.264; Inverse Quantization;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2013 Annual IEEE

Conference_Location

Mumbai

Print_ISBN

978-1-4799-2274-1

Type

conf

DOI

10.1109/INDCON.2013.6726118

Filename

6726118