High rate (3, k) regular LDPC encoder architecture

This paper highlights recent developments in low density parity check (LDPC) encoder. There are some parameters applied in LDPC encoder such as type of LDPC codes, code length, code rate and encoding method. We emphasize that no attempts have been made for the implementation of (3, k) regular LDPC encoder with high code rate (R ≥ 0.875) and few works on flexible LDPC encoder which accommodates various code rates and code lengths. Therefore, this paper proposes a high rate (3, k) regular LDPC encoder architecture which is suitable for high code rate (R ≥ 0.875) applications. Division of workloads between stages is built based on the number of non-zero elements in the parity check matrix (H).