Title :
An ASIC controller for the TMS 320, 2-generation digital signal processor
Author :
Creanza, G. ; Ventrella, O. ; Colangeli, G. ; Subiaco, E.
Author_Institution :
Tecnopolis Casta, Valenzano, Italy
fDate :
29 May-1 Jun 1990
Abstract :
The authors deal with an ASIC that integrates all the glue logic that allows one or more DSPs, organized in a multiprocessor, linear array system, to communicate with their memories, with a host processor and among themselves. This circuit has been developed as a gate array in the ALCATEL FACE research center with the collaboration of TECNOPOLIS CSATA
Keywords :
application specific integrated circuits; digital signal processing chips; logic arrays; multiprocessing systems; storage management chips; ASIC controller; DSP; TMS 320; digital signal processor; gate array; glue logic; linear array system; memory communication; multiprocessor; Application specific integrated circuits; Decoding; Digital signal processing; Digital signal processors; EPROM; Logic arrays; Logic circuits; Random access memory; Read-write memory; Signal generators;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207939
