Title :
VLSI area estimation tolerances-shape function generation vs. floorplanning
Author :
Zimmermann, Gerhard
Author_Institution :
Kaiserslautern Univ., Germany
fDate :
29 May-1 Jun 1990
Abstract :
Area estimation is an important task during the planning of VLSI systems. Several methods have been proposed. But how can one determine the reliability of an estimate? Can an estimate be 100% correct? The answer is no because the design process is not fully predictable. The predictability is an upper limit for the reliability of estimates. Reliability and predictability are defined and examples given. Two very interesting conclusions are drawn: a good estimate of the area of the “best” layout can serve as a termination criterion for design iterations and a good estimate can be more reliable than a prototype layout without iterations
Keywords :
VLSI; circuit layout CAD; CAD; IC layout; VLSI; area estimation tolerances; design iterations; floorplanning; predictability; reliability; shape function generation; termination criterion; Chip scale packaging; Costs; Delay estimation; Fabrication; Logic; Process design; Prototypes; Shape; Space technology; Very large scale integration;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207940
