A floating-point systolic array processing element using serial communication

Author

Davies, T.C. ; Al-Khalili, D. ; Szwarc, V.

Author_Institution

Dept. of Electr. & Comput. Eng., Royal Military Coll. of Canada, Kingston, Ont., Canada

fYear

1990

fDate

29 May-1 Jun 1990

Firstpage

240

Lastpage

243

Abstract

The authors describe the design of a processing element (PE) for systolic array applications. The PE which is configured as a multiplier-accumulator or an inner product step processor, supports most common systolic algorithms in signal processing and matrix arithmetic. Communication with neighbouring PEs is achieved through 18 on-chip serial links, each operating at 50 Mb per second. The 30 K transistor ASIC device is implemented in 2 micron HCMOS gate array technology, packaged in a 48 pin DIP and performs at 10 MFLOPS

Keywords

CMOS integrated circuits; application specific integrated circuits; computerised signal processing; digital arithmetic; microprocessor chips; systolic arrays; 10 MFLOPS; 2 micron; 48 pin DIP; 50 Mbit/s; ASIC device; HCMOS gate array technology; floating-point systolic array; inner product step processor; matrix arithmetic; multiplier-accumulator; processing element; serial communication; signal processing; Array signal processing; Costs; Dynamic range; Electronics packaging; Floating-point arithmetic; Hardware; Military computing; Power system reliability; Signal processing algorithms; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '90

Conference_Location

Paris

Print_ISBN

0-8186-2066-8

Type

conf

DOI

10.1109/EASIC.1990.207947

Filename

207947