DocumentCode
3113736
Title
A flexible gate array RAM compiler with full design tool integration
Author
Steinweg, Russell L. ; Zampaglione, Mike ; Lin, Pei
Author_Institution
VLSI Technol. Inc., San Jose, CA, USA
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
271
Lastpage
276
Abstract
Describes a RAM compiler for gate arrays that is well-integrated into the user design tools. The compiler supports variable aspect ratio, with high-level specification, for flexibility in floorplanning. The various hardware and software features and implementation of the compiler are described, with emphasis on the variable aspect ratio. The user design flow is also described, to show how the compiler fits into the design tools
Keywords
application specific integrated circuits; logic CAD; logic arrays; random-access storage; software tools; RAM compiler; design tool integration; floorplanning; gate arrays; high-level specification; user design tools; variable aspect ratio; Application specific integrated circuits; Design optimization; Hardware; Memory architecture; Productivity; Random access memory; Read-write memory; Routing; Silicon compiler; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207953
Filename
207953
Link To Document