Field modifiable architecture with FPGAs and its design/verification/debugging methodologies

In the age of highly integrated system LSIs, design methodologies for shorter time-to-market and higher re-programmability after the chip fabrications are now key research issues because of the difficulty of complete verification before tape-out of LSI designs. In this paper, we first introduce an IP-based VLSI architecture that consists of a main processor and an additional hardware (both custom hard macros and FPGA on a single chip) specialized to be in charge of the specific instructions. We further replace the controller circuits of the specialized hardware with compact micro-controllers and memories by using IP libraries (hard macros), which results in the increase of the debuggability and the flexibility of design even for computations realized by hard macros. We call the proposed architecture as field modifiable architecture (FMA). Experimental results confirm that our architecture can achieve significant performance improvement in terms of execution cycles and that EC (engineering change) can be successfully accommodated "after" chip fabrications.