A hierarchical behavioural description based CAD system

Author

Nakamura, Yukihiro ; Oguri, Kiyoshi ; Nagoya, Akira ; Nomura, Ryo

Author_Institution

NTT Commun. & Inf. Process. Lab., Kanagawa, Japan

fYear

1990

fDate

29 May-1 Jun 1990

Firstpage

282

Lastpage

287

Abstract

Describes the hierarchical behavioral description language called SFL and its processing system. SFL was developed to aid in the design of the hardware functions and behaviors of ASICs composed solely of clock-synchronized circuits. The main features of SFL are as follows: (1) It is not mixed with connection description, but employs only behavioral description (like procedural description in program language), and it provides hierarchical expression of behavioral description. (2) It permits the description of parallel processing operations by adopting a new hardware task concept. And, (3) it is linked with the behavioral simulator, logic synthesizer, and other components of the processing system. After describing SFL in some detail, a brief explanation of its synthesizer and other processing components is provided, along with its application results in the design of some ASICs

Keywords

application specific integrated circuits; circuit CAD; logic CAD; specification languages; ASICs; SFL; clock-synchronized circuits; hardware task concept; hierarchical behavioral description language; logic synthesizer; parallel processing operations; processing components; Application specific integrated circuits; Communication system control; Constraint optimization; Control design; Delay; Hardware; Humans; Libraries; Logic gates; Parallel processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '90

Conference_Location

Paris

Print_ISBN

0-8186-2066-8

Type

conf

DOI

10.1109/EASIC.1990.207955

Filename

207955