Title :
Fast and area-time efficient Berger code checkers
Author :
Guo, Yu Yau ; Lo, Jien Chung ; Metra, Cecilia
Author_Institution :
Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
Abstract :
In this paper we extend the direct implementation of threshold functions using ratioed FET circuits presented earlier. Such designs are fast, area-time efficient and highly testable with respect to a large class of realistic defects, e.g., resistive breaks and bridges. These threshold functions were then used as core of the new Berger code checkers. For 32-bit checkers, the proposed design has a 59% speed and a 72% area-time improvements over the conventional design assuming 1.2 μm VLSI implementations
Keywords :
VLSI; automatic testing; error detection codes; field effect transistor circuits; integrated circuit testing; threshold logic; 1.2 micron; 32 bit; Berger code checker; VLSI; area-time efficiency; bridges; defects; ratioed FET circuit; resistive breaks; speed; threshold function; Adders; Built-in self-test; Circuits and systems; Encoding; FETs; Hardware; Monitoring; Runtime; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628316
