Anatem Version-2-A CMOS timing analyzer for static CMOS networks

Author

Froidevaux, Michel

Author_Institution

SGS-Thomson Central R&D-CIS, Grenoble, France

fYear

1990

fDate

29 May-1 Jun 1990

Firstpage

354

Lastpage

359

Abstract

A new timing analyzer has been developed. It is able to work at the transistor level, to be back-annotated from the layout, to deal with sequential and combinational logic. The physical way to model the internal timing behavior of a gate, (RC)int, and the use of the least square method to fit experimental and theoretical results, leads to a global accuracy between 10-15% when compared to Eldo [HENN85], for circuits up to 400 transistors, including any kind of static CMOS gates. The number of transistors analyzed is between 100-300 per second, result of first importance for a product used in a timing optimization loop

Keywords

CMOS integrated circuits; combinatorial circuits; least squares approximations; logic CAD; sequential circuits; CMOS timing analyzer; back-annotation; combinational logic; global accuracy; internal timing behavior; least square method; sequential logic; static CMOS networks; timing optimization loop; transistor level; Analytical models; CMOS logic circuits; Computational Intelligence Society; Equations; Least squares methods; Optimization methods; Production; Prototypes; Semiconductor device modeling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '90

Conference_Location

Paris

Print_ISBN

0-8186-2066-8

Type

conf

DOI

10.1109/EASIC.1990.207968

Filename

207968