DocumentCode
3114036
Title
Autodiagnosis speeds turn around time
Author
Ovington, P.
fYear
1990
fDate
29 May-1 Jun 1990
Firstpage
362
Lastpage
364
Abstract
As gate arrays become more complex, the test vector generations effort increases in an alarming fashion. This problem has existed for some time, and there have been many attempts at devising a solution. This paper describes Hitachi´s autodiagnosis concept, which has proved to be enormously successful. Gate array development has now reached a stage of some maturity, and very high densities are being offered by some manufactures. Although, these devices are freely available there still seems some reluctance on the part of potential users to seize the opportunity of designing such devices into their systems. The reason is well understood. As the ratio of gate density of I/O pins increases rapidly, the logic in the core of the array becomes difficult to test. Basically, as the logic becomes more inaccessible from the pins, the controllability and observability fall rapidly
Keywords
automatic testing; logic arrays; logic testing; Hitachi; I/O pins; autodiagnosis concept; controllability; gate arrays; gate density; observability; test vector; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Design engineering; Europe; Logic arrays; Logic devices; Logic testing; Pins;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '90
Conference_Location
Paris
Print_ISBN
0-8186-2066-8
Type
conf
DOI
10.1109/EASIC.1990.207969
Filename
207969
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