Title :
A novel 32 bit RISC architecture unifying RISC and DSP
Author :
Baumhof, Christoph ; Müller, Frank ; Müller, Otto ; Shlett, M.
Author_Institution :
Hyperstone Electron. GmbH, Konstanz, Germany
Abstract :
A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit fixed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed. With the architecture presented, it is proven that a DSP processor can be implemented by strictly using the RISC design philosophy. Besides providing basic 16 bit fixed point functionality, the architecture implements a set of DSP instructions that support an efficient mapping of common DSP algorithms to the processor
Keywords :
digital arithmetic; digital signal processing chips; reduced instruction set computing; 16 bit; 16/32 bit fixed point DSP processor; 32 bit; DSP instructions; RISC design philosophy; basic 16 bit fixed point functionality; common DSP algorithms; novel 32 bit RISC architecture; powerful general purpose microprocessor; Bandwidth; Control systems; Decoding; Digital signal processing; Microcontrollers; Microprocessors; Pipelines; Reduced instruction set computing; Registers; Telecommunication control;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on
Conference_Location :
Munich
Print_ISBN :
0-8186-7919-0
DOI :
10.1109/ICASSP.1997.599836