A dual-issue RISC processor for multimedia signal processing

Author

Sato, H. ; Holmann, E. ; Yoshida, T. ; Matsuo, M. ; Kengaku, T.

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan

Volume

1

fYear

1997

fDate

21-24 Apr 1997

Firstpage

591

Abstract

The paper presents the architecture of a newly developed dual issue RISC processor, D10V, that achieves both high throughput signal processing capability and maintains flexibility for general purpose applications. To achieve adequate performance for signal processing, this RISC processor operates both a MAC unit and a memory access unit in parallel, where two word data memory access is supported. As the result of several benchmarks illustrate, the D10V competes favorably and in some instances outperforms conventional DSPs

Keywords

memory architecture; multimedia computing; reduced instruction set computing; signal processing; D10V; MAC unit; conventional DSPs; dual issue RISC processor; general purpose applications; high throughput signal processing capability; memory access unit; multimedia signal processing; two word data memory access; Arithmetic; Computer architecture; Control systems; Coprocessors; Digital signal processing; Digital signal processing chips; Reduced instruction set computing; Registers; Signal processing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on

Conference_Location

Munich

ISSN

1520-6149

Print_ISBN

0-8186-7919-0

Type

conf

DOI

10.1109/ICASSP.1997.599837

Filename

599837