DocumentCode
3114377
Title
Enhanced interleaved multithreaded multiprocessors and their performance analysis
Author
Zuberek, W.M.
Author_Institution
Dept. of Comput. Sci., Memorial Univ., St John, Alta., Canada
fYear
2004
fDate
16-18 June 2004
Firstpage
7
Lastpage
15
Abstract
In interleaved multithreading, the thread changes in each processor cycle, consecutive instructions are issued from different threads, and no data dependencies can stall the pipeline. Enhanced interleaved multithreading maintains a number of additional threads which are used to replace an active thread when it initiates a long-latency operation. Instruction issuing slots, which are lost in pure interleaved multithreading are thus used by instructions from the new thread. The paper studies performance improvements due to enhanced multithreading by analyzing a timed Petri net model of an enhanced multithreaded architecture at the instruction execution level.
Keywords
Petri nets; discrete event simulation; distributed memory systems; multi-threading; performance evaluation; distributed memory multiprocessors; event-driven simulation; interleaved multithreaded architectures; interleaved multithreaded multiprocessors; interleaved multithreading; long-latency operation; performance analysis; timed Petri nets; Analytical models; Computer science; Delay; Discrete event simulation; Multithreading; Performance analysis; Petri nets; Pipelines; Switches; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Application of Concurrency to System Design, 2004. ACSD 2004. Proceedings. Fourth International Conference on
Print_ISBN
0-7695-2077-4
Type
conf
DOI
10.1109/CSD.2004.1309111
Filename
1309111
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