A method for bounding the effect of DMA I/O interference on program execution time

Author

Huang, Tai-Yi ; Liu, Jane W -S ; Hull, David

Author_Institution

Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

fYear

1996

fDate

4-6 Dec 1996

Firstpage

275

Lastpage

285

Abstract

A DMA controller that operates in the cycle-stealing mode transfers data by “stealing” bus cycles from an executing program. This cycle stealing operation retards the progress of the executing program and extends its execution time. We first present a method that bounds the worst-case execution time of a program executing concurrently with a cycle-stealing DMA I/O operation in the simple case where the execution time of each machine instruction is fixed. We next extend this method to deal with the case of instruction-cache architectures. We demonstrate the effectiveness of our methods by the results of simulations of several programs

Keywords

cache storage; computational complexity; input-output programs; instruction sets; real-time systems; software performance evaluation; DMA I/O operation; DMA controller; bus cycles; cycle stealing operation; cycle-stealing mode; data transfer; executing program; input output operation; instruction-cache architectures; machine instruction; program execution time; simulations; worst-case execution time; Computational modeling; Computer aided instruction; Computer architecture; Computer science; Concurrent computing; Integer linear programming; Interference; Pipelines; Processor scheduling; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Real-Time Systems Symposium, 1996., 17th IEEE

Conference_Location

Los Alamitos, CA

ISSN

1052-8725

Print_ISBN

0-8186-7689-2

Type

conf

DOI

10.1109/REAL.1996.563724

Filename

563724