DocumentCode :
311445
Title :
VLSI architecture for datapath integration of arithmetic over GF(2 m) on digital signal processors
Author :
Drescher, Wolfram ; Bachmann, Kay ; Fettweis, Gerhard
Author_Institution :
Tech. Univ. Dresden, Germany
Volume :
1
fYear :
1997
fDate :
21-24 Apr 1997
Firstpage :
631
Abstract :
This paper examines the implementation of finite field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2m) with m⩽8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the Finite Field operations by adding just a small overhead of logic. We develop division and exponentiation based on multiplication on the algorithm level and present a simple scheme for implementation of all operations on a processor datapath
Keywords :
VLSI; digital arithmetic; digital signal processing chips; VLSI architecture; binary multiplier unit; datapath integration; digital signal processors; division; exponentiation; finite field arithmetic; interconnection structure; multiplication; processor datapath; standard basis; Digital arithmetic; Digital signal processing; Error correction codes; Galois fields; Hardware; Logic; Mobile communication; Signal processing; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on
Conference_Location :
Munich
ISSN :
1520-6149
Print_ISBN :
0-8186-7919-0
Type :
conf
DOI :
10.1109/ICASSP.1997.599847
Filename :
599847
Link To Document :
بازگشت