Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model

Yield enhancement for fault tolerant circuits with redundancy has been widely studied during the last years. Recent manufacturing technologies have brought out steady and significant improvement regarding contamination and defect density and have forced us to re-evaluate the economical advantages of circuits with redundancy. The main goal of this paper is to propose a realistic cost model for fault tolerant chips that includes manufacturing, test and reconfiguration processing steps. We demonstrate, with our model, how optimum and cost-effective redundancy levels can be determined, for a class of fault tolerant architectures, and we compare our results to the usual figure of merit calculation. We demonstrate that wafer test costs can have significant impact on the cost effectiveness of redundant implementation. This model also leads us to show that for a optimized fault tolerant chip, the silicon cost tends to increase as a quasi-linear function of chip area. We finally demonstrate that, considering future fault densities expected for the next decade, economical advantages of redundancy will probably vanish for most integrated circuits when they are implemented with mature processes