Title :
The formal verification chain at BULL
Author :
Madre, Jean-Christophe ; Coudert, Olivier ; Currat, Michel ; Debreil, Alain ; Berthet, Christian
Author_Institution :
BULL Res. Centre, Louveciennes, France
fDate :
29 May-1 Jun 1990
Abstract :
Presents the chain of tools developed at BULL for the verification of circuit designs. For several years, BULL has been a leading site in the field of formal verification of hardware. Until now, the main concern of BULL was in the validation of the VLSI circuits of its mainframe CPUs. The effort is currently extended to board components such as PLDs and ASICs
Keywords :
application specific integrated circuits; circuit CAD; logic CAD; software tools; specification languages; ASICs; PLDs; board components; circuit designs; formal verification chain; verification; Circuit simulation; Circuit synthesis; Computational modeling; Computer aided manufacturing; Design methodology; Design optimization; Formal verification; Hardware design languages; Humans; Very large scale integration;
Conference_Titel :
Euro ASIC '90
Conference_Location :
Paris
Print_ISBN :
0-8186-2066-8
DOI :
10.1109/EASIC.1990.207991
