DocumentCode
3114507
Title
Verification and implementation of delay-insensitive processes in restrictive environments
Author
Kapoor, Hemangee K. ; Josephs, Mark B. ; Furey, Dennis P.
Author_Institution
Center for Concurrent Syst. & VLSI, London South Bank Univ., UK
fYear
2004
fDate
16-18 June 2004
Firstpage
89
Lastpage
98
Abstract
A delay-insensitive module communicates with its environment through wires of unbounded delay. The environment may only need to interact with the module in a restricted way. it is worthwhile taking this into account when synthesising the module because it may allow for a cheaper, faster implementation. Formally, we introduce an operator to DI-algebra which weakens the specification of a module by taking its environment into account. Moreover, the concept of restriction has been built into our translation tool, di2pn (to help in synthesis) and our analysis tool, diana (to perform equivalence and refinement checking).
Keywords
delays; formal specification; formal verification; process algebra; program interpreters; DI-algebra; delay-insensitive processes; di2pn; diana; equivalence checking; module specification; process verification; refinement checking; Delay; Discrete event systems; Logic; Performance analysis; Signal processing; Signal synthesis; Supervisory control; Timing; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Application of Concurrency to System Design, 2004. ACSD 2004. Proceedings. Fourth International Conference on
Print_ISBN
0-7695-2077-4
Type
conf
DOI
10.1109/CSD.2004.1309119
Filename
1309119
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