Title :
Constructing memory layouts for address generation units supporting offset 2 access
Author :
Wess, Bernhard ; Gotschlich, Martin
Author_Institution :
Inst. fur Nachrichtentech. und Hochfrequenztech., Tech. Univ. Wien, Austria
Abstract :
We present an efficient memory layout generation algorithm for digital signal processors (DSPs) which takes advantage of indirect addressing modes with automodify operations. Previously proposed algorithms are optimized with respect to offset 1 access (auto-increment and decrement by 1). Our algorithm is based on a heuristic since the problem of generating optimum memory layouts is NP-complete. However, this algorithm produces optimum results if a bandwidth 2 layout exists for a given program variable access sequence. It is verified by experimental results that our technique achieves significant improvements over existing techniques
Keywords :
circuit layout CAD; digital signal processing chips; integrated memory circuits; memory architecture; NP-complete; address generation units; digital signal processors; indirect addressing; memory layouts; Bandwidth; Concurrent computing; Costs; Digital signal processing; Digital signal processors; Hardware; Registers; Signal generators; Signal processing algorithms;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on
Conference_Location :
Munich
Print_ISBN :
0-8186-7919-0
DOI :
10.1109/ICASSP.1997.599860