Implementation of High Speed Matrix Multiplier Using Vedic Mathematics on FPGA

Author

Mogre, S.V. ; Bhalke, D.G.

Author_Institution

JSPM´s Rajarshi Shahu Coll. of Eng., Pune, India

fYear

2015

fDate

26-27 Feb. 2015

Firstpage

959

Lastpage

963

Abstract

This paper presents unsigned 2x2 High-Speed matrix multiplier using Virtex 5 ML 507 Evaluation Platform (xc5vfx70t-1ff1136) FPGA. The hierarchical structuring has been used to optimize for multipliers using "Urdhava Trigyagbhyam" sutra (vertically and crosswise) which is one of the sutra for Vedic mathematics. Each element of matrix is represented by 16-bit.The coding has been done using VHDL and synthesized using Xilinx 13.2. A concept of design is hierarchical structuring,. This gives less computation time for calculating the multiplication result. This also gives chances for modular design where smaller block can be used to design the bigger one. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling.

Keywords

field programmable gate arrays; matrix multiplication; FPGA Virtex 5 ML 507 evaluation platform; Urdhava Trigyagbhyam sutra; VHDL; Vedic mathematics; Xilinx 13.2; hierarchical structure; high speed matrix multiplier; Adders; Algorithm design and analysis; Clocks; Computer architecture; Field programmable gate arrays; Intellectual property; Field Programmable Gate Array (FPGA); matrix multiplier; vedic Mathematics;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing Communication Control and Automation (ICCUBEA), 2015 International Conference on

Conference_Location

Pune

Type

conf

DOI

10.1109/ICCUBEA.2015.190

Filename

7155988