An Overview of Various Leakage Power Reduction Techniques in Deep Submicron Technologies

The market demand and efficient portable electronic equipment have pushed the industry to produce circuit designs operating at low voltage (LV) for low power (LP) consumption. Reducing the supply voltage reduces the dynamic power quadratic ally and leakage power linearly to the first order. Hence, supply voltage scaling has remained the major focus of the low power design. This has resulted in circuits operating at a supply voltage lower than the threshold voltage of a transistor (i.e. sub threshold region). One of the main contributors for the static power consumption is sub-threshold leakage current, the drain to source current when the gate voltage is smaller than the threshold voltage. As the technology feature size shrink sub threshold leakage current increases exponentially due to the decrease of threshold voltage. According to the International Technology Roadmap for Semiconductors (ITRS) [1], leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink to nanometer regime in deep sub micron technologies. This paper covers critical review of various methods & techniques which are used for reducing the leakage power in VLSI circuits.