Controlled slew rate output buffer

A controlled-slew-rate output buffer has been designed that controls transition edges of an output signal. Thus, AC transients at switching times can be substantially reduced. This eventually reduces switching noise. The theoretical simulations and experimental verifications of this output buffer are presented. A comparison in terms of noise reduction and speed tradeoffs between a controlled and a conventional noncontrolled-slew-rate output buffer is outlined. A test circuit was developed in a 1.25-μm 10 K gate array double-metal CMOS process. The test chip evaluation shows that the magnitude of output ringing in both transition edges is reduced on the controlled slew rate output buffer. The cost of reducing switching noise is sacrificing some speed performance. A TTL input level test shows controlled slew rate output buffers coupled less switching noise to the power buses than the noncontrolled version