Title :
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage
Author :
Pomeranz, Kith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
27 Apr-1 May 1997
Abstract :
We describe an approach to test generation for synchronous sequential circuits that accepts a given test sequence T and targets only faults that could not be detected by the test generation procedure that produced T (hard to detect faults). For every fault f that remains undetected by T, the proposed procedure extracts from T a small number of subsequences (two or three subsequences) that can be combined to form a test sequence for f. It then adds these sequences, if found, to T. By exploring only test sequences that can be extracted from T, a restricted search space for test generation is obtained, and it can be thoroughly explored. Experimental results show that non-trivial numbers of additional faults can be detected by using the proposed procedure to extend a given test sequence T
Keywords :
automatic testing; integrated circuit testing; integrated logic circuits; logic testing; sequences; sequential circuits; EXTEST; fault coverage; synchronous sequential circuits; test generation procedure; test sequences; Circuit faults; Circuit testing; Computational complexity; Electrical fault detection; Fault detection; Performance evaluation; Sequential analysis; Sequential circuits; Space exploration; Synchronous generators;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.600297