Title :
Influence of scribe lanes on wafer potentials and charging damage
Author_Institution :
Wafer Charging Monitors Inc., Woodside, CA, USA
Abstract :
Experimental results show that scribe lane structures can exert a significant influence on surface-substrate potentials and J-V characteristics measured on a wafer in ion-implant processes. This suggests that scribe lane structures used for process control in IC manufacturing, as well as the internal layout of the product itself, may exert significant influence on the surface-to-substrate potentials observed within a die during IC processing, thereby increasing or decreasing the likelihood of device damage
Keywords :
integrated circuit manufacture; ion beam effects; ion implantation; process control; semiconductor doping; substrates; IC manufacturing; IC processing; J-V characteristics; charging damage; device damage; die; internal layout; ion-implant processes; process control; scribe lanes; surface-substrate potentials; wafer; wafer potentials; Current density; Implants; Integrated circuit layout; Manufacturing processes; Plasma devices; Plasma materials processing; Process control; Surface charging; Voltage;
Conference_Titel :
Ion Implantation Technology, 2000. Conference on
Conference_Location :
Alpbach
Print_ISBN :
0-7803-6462-7
DOI :
10.1109/.2000.924216
