• DocumentCode
    3115005
  • Title

    A fast offset-free sample-and-hold circuit

  • Author

    Wang, Fong-Jim ; Temes, Gabor C.

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • fYear
    1988
  • fDate
    16-19 May 1988
  • Abstract
    A sample-and-hold stage is described that uses a CMOS cascode inverter and a novel switching scheme. Since the output voltage need not slew back to the Vos voltage level, the new circuit does not need to have an excessively high slew rate. The experimental results show that a high-speed and small-chip-area sample-and-hold circuit can be obtained when small-geometry (1-μm design rule) devices are available
  • Keywords
    CMOS integrated circuits; invertors; sample and hold circuits; 1 micron; CMOS cascode inverter; fast offset-free sample-and-hold circuit; output voltage; slew rate; small-geometry devices; switching scheme; Application specific integrated circuits; Clocks; Inverters; Parasitic capacitance; Switched capacitor circuits; Switches; Switching circuits; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
  • Conference_Location
    Rochester, NY
  • Type

    conf

  • DOI
    10.1109/CICC.1988.20806
  • Filename
    20806
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3115005