An Efficient Task Placement Method for Reconfigurable FPGA Systems

In recent years, task placement technology for reconfigurable FPGA has been developed into 2-D arrays. In this paper, we propose a methodology to pre-place hardware resource into multi-area to achieve the high utilization of hardware resource and reduce used area. The method solves the task type placement problems on the partial dynamic reconfigurable systems. The proposed placement method can provide multi reconfigurable area reusable which depends on each request to load corresponding reconfigurable module into pre-place reconfigurable area. In this experiment, the task placement into the configuration area is using by the tool of Xilinx Plan Ahead 14.1 [15] to analyze and verify on the Xilinx Virtex-6 system development platform. Comparison of related work, the experiment results shown that the proposed placement methodology increases 20.1% the utilization of hardware resources and reduces 61.1% the area of hardware resources.